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AMD K5
The K5 was AMD's first x86 processor to be developed entirely in-house. Introduced in March 1996, its primary competition was Intel's Pentium microprocessor. The K5 was an ambitious design, closer to a Pentium Pro than a Pentium regarding technical solutions and internal architecture. However, the final product was closer to the Pentium regarding performance, although faster clock for clock compared to the Pentium.
==Technical details==
The K5 was based upon an internal highly parallel 29k RISC processor architecture with an x86 decoding front-end. The K5 offered good x86 compatibility. All models had 4.3 million transistors, with five integer units that could process instructions out of order and one floating point unit. The branch target buffer was four times the size of the Pentium's and register renaming improved parallel performance of the pipelines. The chip's speculative execution of instructions reduced pipeline stalls. It had a 16 KB, four-way set associative instruction cache and an 8 KB data cache. The K5 lacked MMX instructions, which Intel started offering in its Pentium MMX processors that were launched in early 1997.
抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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